Leverages Substrate Design Services to Create Flexible, Low-Cost Packaging Solutions
ESCONDIDO, Calif. – March 29, 2021 – QP Technologies™ (formerly Quik-Pak), a leading provider of innovative microelectronic packaging and assembly solutions, today announced expanded capabilities related to interposer designs for flip-chip and large-cavity packaging as an extension of the company’s substrate design services announced last year.
“Customers that come to us with a flip-chip die often can’t, or don’t want to, expend dollars on creating a redistribution layer [RDL] or a custom package,” said Ken Molitor, QP Technologies’ chief operating officer. “They need a solution that will allow them to package the flip-chip quickly and cost-effectively utilizing existing technology. Our team can help them select the right package and substrate materials – or adapt what they already have and need to continue using – to resolve their packaging challenges.”
A common scenario is that a customer with a validated test platform seeks to make newer die fit into the same package for which its test hardware is already set up. QP Technologies can develop an interposer-based prototype that enables the customer to avoid the time and expense of recreating the test hardware. This allows the reuse of legacy platforms without having to create new, at just 10 to 15 percent the cost and 20 percent the time of a custom package solution – which the company also creates for those who need them.
QP Technologies provides flexible interposer design alternatives for adapting existing packages to redistribute flip-chip connections to wire bonds or shorten bond wire lengths. Modern wire bonders, especially those with the tight pitch required for today’s smaller die, have practical distance limitations for wire spool-out, requiring creative wiring techniques to accommodate larger packages, such as ceramic or plastic pin grid arrays (PGAs). Quik-Pak references the customer’s die bond pad layout to rapidly design an interposer solution that enables flip-chip attach in a package designed for wire bond or minimizes wirelengths enabling interconnections, using organic F4R or silicon substrates, depending on customer requirements.
Applications that can especially benefit from this approach include memory devices and IP cores. Memories utilize expensive testbeds that take a long time to characterize and develop, so the device makers want to retain the PGA format of the template. In the IP space, retesting is required with each new node, so retaining the same package is highly beneficial, especially when validating the IP for multiple nodes or foundries.
“We worked with QP Technologies to develop a solution for continuing to validate our library of cores utilizing existing ceramic, large-cavity PGAs,” noted a senior engineering manager at a leading EDA solutions technology company where time is of the essence. “This approach saved us weeks of development time, allowing us to continue supplying our customers with high-quality, validated IP.”
About QP Technologies
Escondido, Calif.-based QP Technologies (formerly Quik-Pak), a division of Promex Industries, provides wafer preparation, IC packaging and assembly, and substrate design and fabrication services in its 20,000-square-foot ISO 9001:2015/ISO-13485:2016-certified, ITAR-registered facility. The company’s over-molded QFN/DFN packages and pre-molded air-cavity QFN packages offer a fast, convenient solution for customer needs ranging from prototype to volume production. Same-day assembly services reduce customers’ time to market, while advanced assembly services can accommodate such structures as flip-chip, stacked die, SiP, chiplets, MCM and CoB. For more information, visit www.qptechnologies.com, or call 858-674-4676.
Lisa Gillette-Martin. Rosie Medina
Kiterocket QP Technologies